1. Field of the Invention
This invention relates to computer system input/output (I/O) and, more particularly, to I/O and graphics functionality.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many bus systems suffer from several drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. Examples of a shared bus used by I/O devices are a peripheral component interconnect (PCI) bus and an extended peripheral component interconnect (PCI-X) bus.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Additionally, there are systems that use a combination of packet-based communications and bus-based communications. For example, a system may connect to a PCI-X bus and a graphics bus such as AGP. The PCI-X bus may be connected to a packet bus interface that may then translate PCI-X bus transactions into packet transactions for transmission on a packet bus. Likewise the graphics bus may be connected to an AGP interface that may translate AGP transactions into packet transactions. Each interface may communicate with a host bridge associated with one of the processors or in some cases to another peripheral device.
Since transactions associated with many peripheral buses have ordering rules, many of the packet interfaces may have arbitration rules to ensure that the peripheral transactions do not become stalled. I/O devices which use communication protocols may be connected to the system via card slots on buses such as the PCI-X bus and may thus be constrained by the arbitration rules associated with the PCI-X bus. In addition, those I/O devices may have bandwidth requirements that may cause other devices connected to the PCI-X bus to be unintentionally starved or vice versa. SUMMARY OF THE INVENTION
Various embodiments of an I/O node including an integrated graphics engine and an integrated I/O hub are disclosed. In one embodiment, an input/output node for a computer system that is implemented on an integrated circuit chip includes a transceiver unit, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a link of a packet interface. The graphics engine may be coupled to receive graphics packets received by the transceiver unit and may render digital image information in response to receiving the graphics packets. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus, such as a PCI bus for example.
In one particular implementation, the I/O node may include an interface unit also implemented on the integrated circuit chip. The interface unit may be coupled to the transceiver unit and may convey packets between the transceiver unit and each of the graphics engine and the I/O hub.
In another implementation, the I/O node may include a graphics bus interface implemented on the integrated circuit chip. The graphics bus interface may be coupled to receive and to translate the graphics packets into graphics commands suitable for transmission upon a graphics bus.
In a specific implementation, the link of the packet interface may be a point-to-point HyperTransport™ link including a first set of uni-directional wires and a second set of uni-directional wires which may convey packets including control packets and data packets. The control packets may include command packets, info packets and response packets. The control and data packets may share the same wires.
In another embodiment, an input/output node is contemplated that is implemented on an integrated circuit chip that includes a transceiver unit, a graphics bus interface, a graphics engine and an I/O hub. The transceiver unit may receive and transmit packets on a link of a packet interface. The graphics bus interface may be coupled to receive packets including graphics commands and to translate the packets into graphics commands suitable for transmission upon a graphics bus. The graphics engine may be coupled receive the graphics commands via the graphics bus and may render digital image information in response to receiving the graphics commands. The I/O hub may be coupled to receive I/O packets corresponding to packets received by the transceiver unit and may initiate bus cycles corresponding to the I/O packets upon a peripheral bus, such as a PCI bus for example.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.